105 lines
2.2 KiB
Plaintext
105 lines
2.2 KiB
Plaintext
//
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// Generated by NVIDIA NVVM Compiler
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//
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// Compiler Build ID: CL-32688072
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// Cuda compilation tools, release 12.1, V12.1.105
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// Based on NVVM 7.0.1
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//
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.version 8.1
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.target sm_52
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.address_size 64
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// .globl add
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.visible .entry add(
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.param .u64 add_param_0,
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.param .u64 add_param_1
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)
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{
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.reg .pred %p<6>;
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.reg .f32 %f<16>;
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.reg .b32 %r<22>;
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.reg .b64 %rd<25>;
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ld.param.u64 %rd11, [add_param_0];
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ld.param.u64 %rd12, [add_param_1];
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cvta.to.global.u64 %rd1, %rd12;
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cvta.to.global.u64 %rd2, %rd11;
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mov.u32 %r1, %ntid.x;
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mov.u32 %r20, %tid.x;
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setp.gt.s32 %p1, %r20, 99;
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@%p1 bra $L__BB0_7;
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mov.u32 %r12, 99;
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sub.s32 %r13, %r12, %r20;
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div.u32 %r3, %r13, %r1;
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add.s32 %r14, %r3, 1;
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and.b32 %r19, %r14, 3;
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setp.eq.s32 %p2, %r19, 0;
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@%p2 bra $L__BB0_4;
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mul.wide.s32 %rd13, %r20, 4;
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add.s64 %rd24, %rd1, %rd13;
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mul.wide.s32 %rd4, %r1, 4;
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add.s64 %rd23, %rd2, %rd13;
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$L__BB0_3:
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.pragma "nounroll";
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ld.global.f32 %f1, [%rd24];
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ld.global.f32 %f2, [%rd23];
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add.f32 %f3, %f2, %f1;
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st.global.f32 [%rd24], %f3;
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add.s32 %r20, %r20, %r1;
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add.s64 %rd24, %rd24, %rd4;
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add.s64 %rd23, %rd23, %rd4;
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add.s32 %r19, %r19, -1;
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setp.ne.s32 %p3, %r19, 0;
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@%p3 bra $L__BB0_3;
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$L__BB0_4:
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setp.lt.u32 %p4, %r3, 3;
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@%p4 bra $L__BB0_7;
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mul.wide.s32 %rd10, %r1, 4;
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$L__BB0_6:
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mul.wide.s32 %rd14, %r20, 4;
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add.s64 %rd15, %rd2, %rd14;
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add.s64 %rd16, %rd1, %rd14;
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ld.global.f32 %f4, [%rd16];
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ld.global.f32 %f5, [%rd15];
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add.f32 %f6, %f5, %f4;
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st.global.f32 [%rd16], %f6;
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add.s64 %rd17, %rd15, %rd10;
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add.s64 %rd18, %rd16, %rd10;
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ld.global.f32 %f7, [%rd18];
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ld.global.f32 %f8, [%rd17];
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add.f32 %f9, %f8, %f7;
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st.global.f32 [%rd18], %f9;
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add.s32 %r15, %r20, %r1;
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add.s32 %r16, %r15, %r1;
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add.s64 %rd19, %rd17, %rd10;
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add.s64 %rd20, %rd18, %rd10;
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ld.global.f32 %f10, [%rd20];
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ld.global.f32 %f11, [%rd19];
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add.f32 %f12, %f11, %f10;
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st.global.f32 [%rd20], %f12;
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add.s32 %r17, %r16, %r1;
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add.s64 %rd21, %rd19, %rd10;
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add.s64 %rd22, %rd20, %rd10;
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ld.global.f32 %f13, [%rd22];
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ld.global.f32 %f14, [%rd21];
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add.f32 %f15, %f14, %f13;
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st.global.f32 [%rd22], %f15;
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add.s32 %r20, %r17, %r1;
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setp.lt.s32 %p5, %r20, 100;
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@%p5 bra $L__BB0_6;
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$L__BB0_7:
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ret;
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}
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