//
// Generated by NVIDIA NVVM Compiler
//
// Compiler Build ID: CL-32688072
// Cuda compilation tools, release 12.1, V12.1.105
// Based on NVVM 7.0.1
//

.version 8.1
.target sm_52
.address_size 64

	// .globl	add

.visible .entry add(
	.param .u64 add_param_0,
	.param .u64 add_param_1
)
{
	.reg .pred 	%p<6>;
	.reg .f32 	%f<16>;
	.reg .b32 	%r<22>;
	.reg .b64 	%rd<25>;


	ld.param.u64 	%rd11, [add_param_0];
	ld.param.u64 	%rd12, [add_param_1];
	cvta.to.global.u64 	%rd1, %rd12;
	cvta.to.global.u64 	%rd2, %rd11;
	mov.u32 	%r1, %ntid.x;
	mov.u32 	%r20, %tid.x;
	setp.gt.s32 	%p1, %r20, 99;
	@%p1 bra 	$L__BB0_7;

	mov.u32 	%r12, 99;
	sub.s32 	%r13, %r12, %r20;
	div.u32 	%r3, %r13, %r1;
	add.s32 	%r14, %r3, 1;
	and.b32  	%r19, %r14, 3;
	setp.eq.s32 	%p2, %r19, 0;
	@%p2 bra 	$L__BB0_4;

	mul.wide.s32 	%rd13, %r20, 4;
	add.s64 	%rd24, %rd1, %rd13;
	mul.wide.s32 	%rd4, %r1, 4;
	add.s64 	%rd23, %rd2, %rd13;

$L__BB0_3:
	.pragma "nounroll";
	ld.global.f32 	%f1, [%rd24];
	ld.global.f32 	%f2, [%rd23];
	add.f32 	%f3, %f2, %f1;
	st.global.f32 	[%rd24], %f3;
	add.s32 	%r20, %r20, %r1;
	add.s64 	%rd24, %rd24, %rd4;
	add.s64 	%rd23, %rd23, %rd4;
	add.s32 	%r19, %r19, -1;
	setp.ne.s32 	%p3, %r19, 0;
	@%p3 bra 	$L__BB0_3;

$L__BB0_4:
	setp.lt.u32 	%p4, %r3, 3;
	@%p4 bra 	$L__BB0_7;

	mul.wide.s32 	%rd10, %r1, 4;

$L__BB0_6:
	mul.wide.s32 	%rd14, %r20, 4;
	add.s64 	%rd15, %rd2, %rd14;
	add.s64 	%rd16, %rd1, %rd14;
	ld.global.f32 	%f4, [%rd16];
	ld.global.f32 	%f5, [%rd15];
	add.f32 	%f6, %f5, %f4;
	st.global.f32 	[%rd16], %f6;
	add.s64 	%rd17, %rd15, %rd10;
	add.s64 	%rd18, %rd16, %rd10;
	ld.global.f32 	%f7, [%rd18];
	ld.global.f32 	%f8, [%rd17];
	add.f32 	%f9, %f8, %f7;
	st.global.f32 	[%rd18], %f9;
	add.s32 	%r15, %r20, %r1;
	add.s32 	%r16, %r15, %r1;
	add.s64 	%rd19, %rd17, %rd10;
	add.s64 	%rd20, %rd18, %rd10;
	ld.global.f32 	%f10, [%rd20];
	ld.global.f32 	%f11, [%rd19];
	add.f32 	%f12, %f11, %f10;
	st.global.f32 	[%rd20], %f12;
	add.s32 	%r17, %r16, %r1;
	add.s64 	%rd21, %rd19, %rd10;
	add.s64 	%rd22, %rd20, %rd10;
	ld.global.f32 	%f13, [%rd22];
	ld.global.f32 	%f14, [%rd21];
	add.f32 	%f15, %f14, %f13;
	st.global.f32 	[%rd22], %f15;
	add.s32 	%r20, %r17, %r1;
	setp.lt.s32 	%p5, %r20, 100;
	@%p5 bra 	$L__BB0_6;

$L__BB0_7:
	ret;

}