feat(ccd): add dual-clock field sampling

Co-authored-by: Cursor <cursoragent@cursor.com>
2026-07-22 14:07:05 +08:00
parent c9ce3e6dcb
commit 8d760145de
8 changed files with 489 additions and 27 deletions
@@ -28,6 +28,10 @@ scripts/collect_*.py  →   detect_period.py     →   compute_correction_
                                                                                (CPU)
 ```

+## Dual-clock field sampling
+
+Legacy DRL 的控制时钟与 DDF 保存时钟必须独立：模型仍只在固定控制周期边界读取完整 observation 和预测动作，DDF 可以在周期内任意 lattice step 读取。通用 API、OID 复用方式、输出时间轴合同和 GPU A/B 结果见 [`DUAL_CLOCK_SAMPLING.md`](DUAL_CLOCK_SAMPLING.md)。
+
 ## Key Conventions

 ### Geometry (unified 2026-06-25)