Test-only, on c6d5dc1. DenseBlockedRouteParity runs the same configuration,
initial state, body/Jet schedule and tilings on D/D [None, None], D/B
[None, FINE_BLOCK] and B/B [(12, 8), FINE_BLOCK], periodic and
slot/reservoir, for body-free, passive circle, actuated circle (+/-) and a
velocity Jet with an amplitude switch: every public and owner array must
match in FP32 bits and NaN masks at steps 0, 1, 2, 8 and after
re-initialize, and the D/B and B/B raw-exchange ledgers (last base step and
last substep) must be equal. No tolerance.
test_route_capability_matrix checks before CUDA what the dense route
rejects (raw exchange on a dense body level, shifted, projected, channel,
several L1 rectangles, depth >= 3 dense). The module docstring holds the
supported/unsupported table and the parked cases (MRT covered elsewhere,
shifted and depth >= 3 have no dense route, several bodies later).
Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
