Saved-case static SASS readout, 2026-10-22. No GPU execution.

Historical revision: 9805383f9c50d867e8555471baf5dbda8333a652
Saved inputs/PTX root (Horsea):
 /home/frank14f/CelerisLab/output/validation-campaign-9805383-20261018/parity_output/targeted/
New evidence root (Horsea):
 /home/frank14f/CelerisLab-release-evidence-20261020/srt-sass-9805383-20261022/

PROVENANCE
No cubin/fatbin/sass was saved in parity_output. Historical compiler_v2.py
compiled nvcc -ptx -arch=sm_70 --use_fast_math, loaded with module_from_file,
and cleaned its private build directory; it did not use PyCUDA's cubin cache.
Read-only search of the existing ~/.nv/ComputeCache covered 1536 data entries.
Existing cache /home/frank14f/.nv/ComputeCache/7/8/841159509b51c2 contains the
entire saved uniform PTX byte-for-byte at offset 58, ELF at offset 136224.
No complete blocks PTX match, including comment/blank-line normalization.
Uniform cache usage is not linked to the historical run by a receipt.
Cache mtime_ns=1792502748041641923; header Dec 30 2024 17:14:06 HOST64 sm_70.
Thus this is a matching existing cached binary, not a proven original-run binary.

Both saved PTX files were assembled OFFLINE with existing
 /usr/local/cuda/bin/ptxas -arch=sm_70 -v INPUT -o EXTERNAL_OUTPUT
ptxas 12.4.131 / CL-34097967; cuobjdump 12.4.127. Driver 550.144.03.
Horsea V100 architecture is sm_70. No CUDA context/kernel was created.
Uniform rebuilt cubin is byte-identical to extracted matching cache ELF:
 a3af0e45c2698a18f7a06ba5aa0bb8dc6602848c2be9712b0162bd01f050d065
Blocks rebuilt cubin SHA256:
 c17ded09f6a5e819617bec7949e3e910d9ac53476be47b5545b8a09983e96e23
OneStep 39 registers; BlockChannelStep 32 registers; both zero spills/stack.
Blocked SASS below is REBUILT, not an identified original executed binary.

DEPENDENCY MAPPING AT BULK (y=10,x=3), q4
Saved configuration: FP32 shifted D2Q9 SRT, nx24 ny20, omega1.25,
uniform inlet, clamp true, damping0.5, block20x24, zero force, step6.
Input step5 uniform and blocked arrays are byte-identical.
Uniform branch: BB5_6 -> BB5_11 -> BB5_14 -> BB5_16 (force branch skipped).
Blocked branch: BB6_3 -> BB6_6 -> BB6_7 -> BB6_12 (wall/inlet/outlet skipped).

PTX rho accumulation is q0+q1, +q2,...,+q8,+1 in both modules.
PTX uniform L1624 rho=%f51, L1625 rcp.approx.ftz=%f242;
     blocked L1342 rho=%f202, L1344 rcp.approx.ftz=%f204.
Both lower to MUFU.RCP: uniform 0x1410 R23,R19; blocked 0x1630 R2,R3.
Momentum order jx=q1-q2+q5-q6+q7-q8; jy=q3-q4+q5-q6-q7+q8.
Uniform 0x1450 R26=ux, 0x1470 R23=uy; blocked 0x1640 R9=uy, 0x1650 R7=ux.

Uniform square sum: PTX L1653 mul ux²; L1654 fma uy*uy+rounded ux².
 SASS 0x14b0 FMUL.FTZ R0, R26, R26;
      0x1700 FFMA.FTZ R21, R23, R23, R0;       // S=fma(uy,uy,R(ux²))
      0x1710 FMUL.FTZ R23, R23, 3;            // cu_y=3*uy
      0x17c0 FMUL.FTZ R29, R23, R23;          // cu_y²
Blocked square sum: PTX L1360 mul uy²; L1361 fma ux*ux+rounded uy².
 SASS 0x1660 FMUL.FTZ R6, R9, R9;
      0x1680 FFMA.FTZ R21, R7, R7, R6;        // S=fma(ux,ux,R(uy²))
      0x1690 FMUL.FTZ R9, R9, 3;              // cu_y=3*uy
      0x16f0 FMUL.FTZ R19, R9, R9;            // cu_y²

KEY EXTRA CONTRACTION (both binaries):
Uniform PTX L1655 c3=mul(S,-1.5) + L1679 sub(c3,cu_y)
  -> SASS 0x1820 FFMA.FTZ R30, R21, -1.5, -R23;
Blocked PTX L1362 c3=mul(S,-1.5) + L1383 sub(c3,cu_y)
  -> SASS 0x1710 FFMA.FTZ R24, R21, -1.5, -R9;
No separately rounded c3 is consumed by the q4 SASS dependency chain.

Half cu² addition:
 Uniform PTX L1680 -> 0x1880 FFMA.FTZ R29, R29, 0.5, R30;
 Blocked PTX L1384 -> 0x1760 FFMA.FTZ R11, R19, 0.5, R24;
rho-1 remains separately rounded:
 Uniform PTX L1660 -> 0x18f0 FADD.FTZ R30, R19, -1;
 Blocked PTX L1357 -> 0x17b0 FADD.FTZ R6, R3, -1;
Shifted equilibrium inner rho*bracket+(rho-1):
 Uniform PTX L1681 -> 0x19b0 FFMA.FTZ R29, R19, R29, R30;
 Blocked PTX L1385 -> 0x1910 FFMA.FTZ R23, R3, R11, R6;
Weight multiplication is a separate FMUL in both (w=0x3de38e39):
 Uniform PTX L1682 -> 0x1a40 FMUL.FTZ R29, R29, 0.11111111193895339966;
 Blocked PTX L1386 -> 0x1980 FMUL.FTZ R23, R23, 0.11111111193895339966;
q4 collision and store:
 Uniform PTX L1769-1771,1793 ->
  0x18c0 FMUL.FTZ R12, R25, R12;              // ctau * zero force
  0x1aa0 FFMA.FTZ R12, R29, R15, R12;        // feq4 * omega + zero
  0x1b40 FFMA.FTZ R9, R9, R0, R12;           // oldq4*(1-omega) + inner
  0x1c00 STG.E.SYS [R4+0x1e00], R9;
 Blocked PTX L1415,1424-1425,1444 ->
  0x1810 FMUL.FTZ R7, RZ, R25;              // zero * ctau
  0x19f0 FFMA.FTZ R26, R23, R2, R7;        // feq4 * omega + zero
  0x1a60 FFMA.FTZ R13, R13, R9, R26;       // oldq4*(1-omega) + inner
  0x1b40 STG.E.SYS [R2+0x23c0], R13;
Uniform omega=R15, ctau=R25, oneMinusOmega=R0. Blocked omega=R2,
ctau=R25, oneMinusOmega=R9. Both ctau are native FFMA(omega,-.5,1),
including contraction of the blocked PTX mul/sub pair; .375 is exact here.

EXACT HOST REPLAY OF THIS SASS CONTRACTION
Uses the existing exact Fraction binary32 RNE calculator, independently checked
against libm.fmaf (31 matching fused operations including prior replay/selftest).
IEEE reciprocal SUBSTITUTE 3f79a3fb; rho3f8342bf; ux3c893f98; uyb8887923.

                  uniform path         blocked path
square sum        39932ad3              39932ad2
fma(S,-1.5,-uy3)   b96ccac5              b96ccac2
half-cu² bracket  b96cc5a7              b96cc5a4
rho*B+(rho-1)     3cceca24              3cceca25
feq4              3b37d020              3b37d021
inner collision   3b65c428              3b65c429
output            3b4794a0              3b4794a1
saved output      3b4794a0              3b4794a1

This reproduces BOTH saved output bit patterns on the unchanged saved input.
The previous PTX-operation replay rounded c3 separately and therefore missed
the second contraction; all its variants ended at 3b4794a1.
No nonzero subnormal intermediate in these CPU calculations. GPU approximate
reciprocal remains unrecorded; IEEE substitution is not a measured MUFU result.
This is a concrete static mechanism plus exact host reproduction, not proof of
the historical binary's actual intermediate registers or a universal cause.
No reciprocal-neighborhood claim is made. No GPU test, instrumentation, source
change, integration, assertion change, or historical evidence modification.
